A PROFICIENT DESIGN AND ANALYSIS OF SEQUENCE GENERATOR USING TRELLIS CODE

Authors

  • M. Yuvaraju Assistant Professor, Electrical and Electronics Engineering, Anna University Regional Campus, Coimbatore, Tamil Nadu, India. Author
  • S.K. Sujitha PG Scholar, Electrical and Electronics Engineering, Anna University Regional Campus, Coimbatore, Tamil Nadu, India. Author

Keywords:

CDMA, Field Programmable Gate Array, FIR Filter, MAC, Statistical Error Compensation

Abstract

Major communications systems that rely on Code Division Multiple Access (CDMA) spreads the bandwidth of the transmitted signal over a wide frequency band by employing pseudorandom code sequences. Transposed FIR filter is a variation of the direct FIR model. A direct form FIR filter can be altered into a Transposed FIR filter by exchanging input and output, changing the direction of signal flow and also by substituting an adder by a fork and vice versa. Classic analog filters are rapidly getting replaced by digital filters. Digital filters can be implemented using Programmable DSP with MAC. Field Programmable Gate Array (FPGA) technology will be able to provide multiple MACs for high-bandwidth signal processing applications to achieve the desired throughput. Xilinx tool can be used to design the conventional filter and pseudo random sequence generator. The errors in hardware are treated by SEC as noise in communication networks and for compensation of errors, robust elimination technique can be employed when compared with other conventional methods.

References

Wireless LAN Medium Access Control (MAC) and Physical Layer (PHY) Specifications, ANSI/IEEE Standard 802.11:1999 (E) Part II, ISO/IEC 880 211, 1999.

CDMA2000 Wireless IP Network Standard, 3GPP2 Standard TIA/EIA/IS-835B, 2000.

S. Sheng, L. Lynn, J. Peroulas, K. Stone, I. O‟Donnell, and R. Brodersen, “A Low-Power CMOS Chipset for Spread Spectrum Communications,” in Proc. IEEE Int. Solid-State Circuits Conf., Feb. 1996, pp. 346–347.

W. Namgoong and T. Meng, “Minimizing Power Consumption in Direct Sequence Spread Spectrum Correlators by Resampling IF Samples-Part I: Performance Analysis,” IEEE Trans. Circuits Syst., vol. 48, no. 5, pp. 450–459, May 2001.

R. Hegde and N. Shanbhag, “A Voltage Overscaled Low-Power Digital Filter IC,” IEEE J. Solid-State Circuits, Vol. 39, No. 2, pp. 388–391, Feb. 2004.

S. Das et al., “A self-tuning DVS Processor Using Delay-Error Detection and Correction,” IEEE J. Solid-State Circuits, Vol. 41, No. 4, pp. 792–804,Apr. 2006.

D. Blaauw et al., “Razor II: In Situ Error Detection and Correction for PVT and SER Tolerance,” in Proc. ISSCC, Feb. 2008, pp. 400–622.

J. Tschanz et al., “A 45nm Resilient and Adaptive Microprocessor Core for Dynamic Variation Tolerance,” in Proc. ISSCC, Feb. 2010, pp. 282–283.

G. Varatkar, S. Narayanan, N. Shanbhag, and D. Jones, “Stochastic Networked Computation,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., Vol. 18, No. 10, pp. 1421–1432, Oct. 2010.

D. Senderowicz et al., “A 23 mw 256-tap 8 msample/s QPSK Matched Filter for DS-CDMA Cellular Telephony using Recycling Integrator Correlators,” in Proc. ISSCC, 2000, pp. 354–355.

S. Kim and B. Daneshrad, “A 100 μW, 20 Mcps Versatile Correlator Chip for Third Generation WCDMA systems,” in Proc. Asilomar Conf.Signals, Syst., Comput., Vol. 1. Oct. 1999, pp. 130–134.

K. Onodera and P. Gray, “A 75-mW 128-MHz DS-CDMA Baseband Demodulator for HighSpeed Wireless Applications [LANs],” IEEE J. Solid-State Circuits, Vol. 33, No. 5, pp. 753– 761, May 1998.

P. Huber, Robust Statistics. New York, NY, USA: Wiley, 1981.

C. Lee and C. Jen, “BitSliced Median Filter Design Based on Majority Gate,” IEE Proc. Circuits, Devices Syst., Vol. 139, No. 1, pp. 63–71, Feb. 1992.

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Published

2024-07-05

How to Cite

M. Yuvaraju, & S.K. Sujitha. (2024). A PROFICIENT DESIGN AND ANALYSIS OF SEQUENCE GENERATOR USING TRELLIS CODE. INTERNATIONAL JOURNAL OF RESEARCH IN COMPUTER APPLICATIONS AND INFORMATION TECHNOLOGY (IJRCAIT), 4(3). http://ijrcait.com/index.php/home/article/view/34