ACCELERATING FUNCTIONAL COVERAGE CLOSURE THROUGH ITERATIVE MACHINE LEARNING - Kaushik Velapa Reddy, (INTERNATIONAL JOURNAL OF RESEARCH IN COMPUTER APPLICATIONS AND INFORMATION TECHNOLOGY (IJRCAIT), 2024)
This article presents a novel machine learning-based method for closing functional coverage in System-on-Chip (SoC) verification that improves coverage quality and drastically cuts down on verification cycle time. To automatically detect coverage gaps and provide focused test cases, it introduces a unique framework that blends deep neural networks with iterative learning algorithms, building on well-established coverage-directed test generation approaches. Five industrial SoC designs with gates ranging from 2M to 15M are used for evaluation. The results show a 52% decrease in verification effort compared to previous methods and a 15% improvement in functional coverage, with 99.2%. Using a three-phase learning architecture—adaptive test generation, initial coverage analysis, and continual refinement—the suggested method accelerates coverage convergence for complex corner instances by 3.8 times. This approach consistently outperforms standard coverage closure techniques, especially when identifying and targeting hard-to-reach coverage points that usually require extensive manual intervention, as confirmed by an analysis of over 50,000 simulation runs across various design configurations. The system's use at three significant semiconductor businesses further validates the results, reducing the manual test generation effort by 71% while increasing overall verification confidence through more thorough coverage of corner cases. The results show that machine learning-driven verification closure is feasible in actual industrial environments and provides a foundation for future automation of hardware verification processes.